The trend for the need of larger and faster SRAMs operating at lower supply voltage continues to dominate system design progression. SRAMs are used in are used in processor caches with frequencies reaching 4 GHz. SRAM access time, dominated by bit-line loading and bit-cell read current is a critical parameter.
The bit-line impedance and the bit-cell read strength follow an intra-chip distribution that must be taken into account in SRAM design to ensure reasonable yield of electronic components that meet all the system speed requirements expected of an SRAM. Therefore knowledge of the distribution of bit-cell read time dominated by bit-line impedance and bit-cell read current is critical for SRAM design. This criticality increases with SRAM array size.
Prior art methods for the dynamic characterization of the read time and read current of SRAM bit-cells utilize ring oscillators and pulse stretching circuitry in the path of the bit-line/bit-cell combination read path.